1. Field of the Invention
The invention relates to a semiconductor integrated circuit chip, and more particularly to a reduction in clock skew of clock pulses provided to an element of a semiconductor integrated circuit chip.
2. Description of the Related Art
With development of technology for fabricating a smaller and smaller semiconductor device with regard to size, a circuit scale required for a semiconductor integrated circuit chip becomes larger, and higher complexity in function and higher speed in operation are required. For meeting these requirements, internal wirings in a semiconductor integrated circuit chip have become longer and longer in length between the functional blocks constituting parts of the chip and a dock driver distributing operation clocks to the functional clocks, resulting in skew that may be generated because of a difference in clock wiring length.
As is well known to those skilled in the art, clock skew means a difference between a time at which a clock or timing pulse is expected to arrive at a functional block and a time at which a clock has actually arrived at a functional block. The reason why clock skew is generated is explained as follows. For instance, when comparing a flip-flop disposed closest to a clock driver with a flip-flop disposed most remote from the clock driver, they have different time constants of wiring resistance and through hole resistance to wiring capacity and flip-flop input capacity. Thus, the clocks are out of phase at input terminals of respective flip-flops.
Accordingly, it is quite important to eliminate clock skew in order to operate a chip at a higher rate. Various attempts have been made to decrease clock skew. For instance, divided clock lines have been designed to have a common length, or a clock line has been designed to be quite short in length. One of the methods of reducing clock skew has been suggested in Japanese Unexamined Patent Publication No. 59-136948, which will be explained hereinbelow.
FIG. 1 is an enlarged perspective view illustrating a circuit for preventing occurrence of clock skew in an integrated circuit chip, suggested in the Publication No. 59-136948. The illustrated semiconductor integrated circuit 200 includes a silicon substrate 18, a clock distributing line 12 formed on the substrate 18, first and second electrically conductive lines 14 and 15 disposed so that the clock distributing line 12 is interposed between the first and second electrically conductive lines 14 and 15, and two pulse carry lines 11 and 13 disposed outside the first and second electrically conductive lines 14 and 15, respectively, a ground bus 16, and a wire for bonding the ground bus 16 to an external electrode 17. The first and second electrically conductive lines 14 and 15 are directly, electrically connected to the ground bus 16 so that the first and second lines 14 and 15 have a grounded level. By disposing the electrically conductive lines 14 and 15 so that they interpose the clock distributing line 12 therebetween, the clock distributing line 12 is electrostatically shielded from the pulse carry lines 11 and 13.
In other words, the clock distributing line or timing pulse distributing line 12 is shielded by disposing it between the first and second lines 14 and 15, both having a fixed dc level. By shielding the timing pulse distributing line 12, a side capacity between sides of those lines 12, 14, 15 is varied. Assuming that a capacity between the timing pulse distributing line 12 and the first and second electrically conductive lines 14 and 15 is represented as Cs and a capacity between the timing pulse distributing line 12 and the silicon substrate 18, arranged in insulating relation with each other, is represented as Cb, the side capacity is maximized when a potential between the lines 12 and 14 has a different sign as that of a potential between the lines 12 and 15. The maximum side capacity is equal to (4Cs+Cb). On the other hand, the side capacity is minimized when a potential between the lines 12 and 14 has the same sign as that of a potential between the lines 12 and 15. The minimum side capacity is equal to Cb.
According to the above mentioned Publication No. 59-136948, a capacity between the timing pulse distributing line 12 and the first and second lines 14, 15 is varied to nearly 3 pF, thereby ensuring almost zero clock skew.
In the above mentioned Publication, by disposing the timing pulse distributing line 12 in parallel between the lines having a fixed dc level or power distributing lines 14 and 15, there is produced a difference in potential between the timing pulse distributing line 12 and the lines 14, 15. As the result, a capacity between the lines 12, 14, 15 is varied to thereby ensure a quite small side capacity. Accordingly, the time constant on signal transmission through the timing pulse distributing line can be decreased to thereby make it possible to reduce clock skew down to almost zero.
In general, the power distributing lines 14 and 15 are required to have a small resistivity in order to ensure a large current capacity and small voltage drop. If a line has a uniform thickness, the resistivity of the line is dependent on a cross-sectional area thereof. Thus, a power distributing line is generally designed to have a larger width. Hence, unless the power distributing lines are efficiently arranged, the lines occupy a larger area with the result being a larger area of an integrated circuit chip.
In the prior semiconductor integrated circuit chip illustrated in FIG. 1, the power distributing lines 14 and 15 arranged in parallel with the timing pulse distributing line 12 are designed to have the same width as that of an ordinary signal line to thereby make a cross-sectional area thereof smaller. However, it is necessary for the lines 14 and 15 to at least partially have a wider portion for making a through hole contact. The through hole contact requires a much larger area than that of an ordinary signal line, resulting in that the contact has to have a large wiring area therearound.